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| NCP5211A Low Voltage Synchronous Buck Controller The NCP5211A is a low voltage synchronous buck controller. It contains all required circuitry for a synchronous buck converter using external N-Channel MOSFETs. High current internal gate drivers are capable of driving low RDS(on) NFETs for better efficiency. The NCP5211A is in a 14 pin package to minimize PCB area. The NCP5211A provides overcurrent protection, undervoltage lockout, soft start and built in adaptive nonoverlap. The NCP5211A is adjustable over a frequency range of 150 kHz to 750 kHz. This gives the designer more flexibility to make efficiency and component size compromises. The NCP5211A will operate on a single supply or a separate boost supply. Features http://onsemi.com MARKING DIAGRAM 14 SOIC-14 D SUFFIX CASE 751A 1 B WL Y WW = Assembly Location = Wafer Lot = Year = Work Week NCP5211A BWLYWW * Switching Regulator Controller - N-Channel Synchronous Buck Design - 1.0 Amp Gate Drive Capability - 200 ns Transient Response - Programmable Operating Frequency of 150 kHz-750 kHz - 0.8 V 1% Internal Reference - Lossless Inductor Sensing Overcurrent Protection - Cycle-by-Cycle Short Circuit Protection - Programmable Soft Start - 40 ns GATE Rise and Fall Times (3.3 nF Load) - 70 ns Adaptive FET Nonoverlap Time - Differential Remote Sense Capability * System Power Management - Operation with a Conversion Rail of 5.0 V or 12 V - Undervoltage Lockout - On/Off Control Through Use of the COMP Pin - Max Duty Cycle Clamped to 70% for Forward Converter Control Applications PIN CONNECTIONS 1 GATE(H) BST LGND VFFB VFB COMP SGND PGND GATE(L) VC IS+ IS- VCC ROSC ORDERING INFORMATION Device NCP5211AD NCP5211ADR2 Package SO-14 SO-14 Shipping 55 Units/Rail 2500 Tape & Reel * * * * Set Top Devices Forward Converters Buck Converters Point of Load Regulation For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2003 1 December, 2003 - Rev. 3 Publication Order Number: NCP5211A/D NCP5211A 5.0 V + 100 F/10 V x 3 NTMS7N03 0.1 F VC VCC COMP 0.1 F 51 k 0.1 F ROSC NCP5211A IS+ IS- SGND LGND 10 VFFB VFB 2.15 k 1.0 k 1.0% 680 pF SENSE- NOTE: Resistance in Ohms 1.0% SENSE+ BST GATE(H) GATE(L) PGND NTMS7N03 0.1 F 4.7 k + 2.9 H 2.5 V/8 A +VOUT 100 F/10 V x 2 10 -VOUT Return Figure 1. Application Diagram, 5.0 V to 2.5 V/8 A Converter with Differential Remote Sense MAXIMUM RATINGS* Rating Operating Junction Temperature, TJ Lead Temperature Soldering: Storage Temperature Range, TS Package Thermal Resistance: Junction-to-Case, RJC Junction-to-Ambient, RJA ESD Capability - All pins except ROSC (Human Body Model) (Machine Model) ESD Capability - ROSC Pin Only (Human Body Model) (Machine Model) JEDEC Moisture Sensitivity 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed by not exceeding 150C TJ. Reflow: (SMD styles only) (Note 1) Value 150 230 peak -65 to +150 30 125 2.0 200 500 150 Level 1 Unit C C C C/W C/W kV V V V - http://onsemi.com 2 NCP5211A MAXIMUM RATINGS (Voltage with respect to Logic Ground) Pin Name IC Power Input Power input for the low side driver Power Supply input for the high side driver Compensation Capacitor Voltage Feedback Input Oscillator Resistor Fast Feedback Input High-Side FET Driver Pin Symbol VCC VC BST VMAX 16 V 16 V 20 V VMIN -0.3 V -0.3 V -0.3 V ISOURCE N/A N/A N/A ISINK 50 mA DC 1.5 A Peak, 200 mA DC 1.5 A Peak, 200 mA DC COMP VFB ROSC VFFB GATE(H) 6.0 V 6.0 V 6.0 V 6.0 V 20 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -2.0 V for 50 ns -0.3 V -2.0 V for 50 ns -0.3 V -0.3 V -0.2 V N/A -0.2 V 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.5 A Peak 200 mA DC 1.5 A Peak 200 mA DC 1.0 mA 1.0 mA 1.5 A Peak, 200 mA DC 100 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.5 A Peak 200 mA DC 1.5 A Peak 200 mA DC 1.0 mA 1.0 mA N/A N/A 1.0 mA Low-Side FET Driver GATE(L) 16 V Positive Current Sense Negative Current Sense Power Ground Logic Ground Sense Ground IS+ IS- PGND LGND SGND 6.0 V 6.0 V 0.2 V N/A 0.2 V ELECTRICAL CHARACTERISTICS (-40C < TA < 85C; -40C < TJ < 125C; 4.5 V < VCC, VC < 14 V; 7.0 V < BST < 20 V; CGATE(H) = CGATE(L) = 3.3 nF; ROSC = 51 k; CCOMP = 0.1 F, unless otherwise specified.) Characteristic Error Amplifier VFB Bias Current COMP Source Current COMP SINK Current Open Loop Gain Unity Gain Bandwidth PSRR @ 1.0 kHz Output Transconductance Output Impedance Reference Voltage VFB = 0 V VFB = 0.6 V VFB = 1.2 V (Note 2) C = 0.1 F, (Note 2) (Note 2) (Note 2) (Note 2) -0.1 V < SGND < 0.1 V, COMP = VFB, Measure VFB to SGND VFB = 0.6 V VFB = 1.2 V - - -40 TJ 125C 25 TJ 110C - 15 15 - - - - - 0.788 0.792 2.5 - 500 0.2 0.1 30 30 98 50 70 32 2.5 0.8 0.8 3.0 0.1 750 0.4 1.0 60 60 - - - - - 0.812 0.808 - 0.2 1000 0.6 V V A V A A A dB kHz dB mmho M V Test Conditions Min Typ Max Unit COMP Max Voltage COMP Min Voltage COMP Discharge Current in UVLO COMP Threshold to Start Gate Drive 2. Guaranteed by design. Not tested in production. http://onsemi.com 3 NCP5211A ELECTRICAL CHARACTERISTICS (continued) (-40C < TA < 85C; -40C < TJ < 125C; 4.5 V < VCC, VC < 14 V; 7.0 V < BST < 20 V; CGATE(H) = CGATE(L) = 3.3 nF; ROSC = 51 k; CCOMP = 0.1 F, unless otherwise specified.) Characteristic GATE(H) and GATE(L) High Voltage (AC) GATE(L), GATE(H) 0.5 nF < CGATE(H) = CGATE(L) < 10 nF GATE(L) or GATE(H) 0.5 nF < CGATE(H); CGATE(L) < 10 nF VC = BST = 10 V, Measure: 1.0 V < GATE(L) < 9.0 V, 1.0 V < GATE(H) < 9.0 V VC = BST = 10 V, Measure: 1.0 V < GATE(L) < 9.0 V, 1.0 V < GATE(H) < 9.0 V GATE(H) < 2.0 V, GATE(L) > 2.0 V GATE(L) < 2.0 V, GATE(H) > 2.0 V Resistance to PGND VC - 0.5 BST - 0.5 - - - - V Test Conditions Min Typ Max Unit Low Voltage (AC) Rise Time - 40 0.5 80 V ns Fall Time - 40 80 ns GATE(H) to GATE(L) Delay GATE(L) to GATE(H) Delay GATE(H)/(L) Pull-Down Overcurrent Protection Current Limit Threshold IS+ Bias Current IS- Bias Current PWM Comparator Transient Response PWM Comparator Offset Artificial Ramp VFFB Bias Current VFFB Max Input Minimum Pulse Width Oscillator Switching Frequency ROSC Voltage Max Duty Cycle General Electrical Specifications VCC Supply Current BST Supply Current VC Supply Current Start Threshold Stop Threshold Hysteresis Sense Ground Current 40 40 20 70 70 50 110 110 115 ns ns k 0 V < IS+ < 4.5 V, 0 V < IS- < 4.5 V 0 V < IS+ < 4.5 V 0 V < IS- < 4.5 V 54 -1.0 -1.0 60 0.1 0.1 66 1.0 1.0 mV A A COMP = 0 - 1.5 V, VFFB, 20 mV overdrive VFB = VFFB = 0 V; Increase COMP until GATE(H) starts switching Duty Cycle = 70% (Note 3) VFFB = 0 V (Note 3) - - 0.425 30 - 1.1 - 100 0.475 55 0.1 - - 200 0.525 80 1.0 - 200 ns V mV A V ns ROSC = 51 k - VCOMP > VFFB + 1.0 V 270 1.21 65 300 1.25 70 330 1.29 75 kHz V % COMP = 0 V (no switching) COMP = 0 V (no switching) COMP = 0 V (no switching) GATE(H) Switching, COMP Charging GATE(H) Not Switching, COMP Not Charging Start-Stop - - - - 4.03 3.89 100 - 7.0 2.0 2.0 4.18 4.04 140 0.15 8.3 3.0 3.0 4.33 4.19 180 1.00 mA mA mA V V mV mA 3. Guaranteed by design. Not tested in production. http://onsemi.com 4 NCP5211A PACKAGE PIN DESCRIPTION PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIN SYMBOL GATE(H) BST LGND VFFB VFB COMP SGND ROSC VCC IS- IS+ VC GATE(L) PGND FUNCTION High Side Switch FET driver pin. Capable of delivering peak currents of 1.0 A. Power supply input for the high side driver. Reference ground. All control circuits are referenced to this pin. IC substrate connection. Input for the PWM comparator. Error amplifier input. Error Amp output. PWM Comparator reference input. A capacitor to LGND provides error amp compensation. Internal reference is connected to this ground. Connect directly at the load for ground remote sensing. A resistor from this pin to SGND sets switching frequency. Input Power Supply Pin. It supplies power to control circuitry. A 0.1 F decoupling cap is recommended. Negative input for overcurrent comparator. Positive input for overcurrent comparator. Power supply input for the low side driver. Low Side Synchronous FET driver pin. Capable of delivering peak currents of 1.0 A. High Current ground for the GATE(H) and GATE(L) pins. 0.5 V - - PWM Comparator Ramp + VFFB + PWM FF Reset Dominant R STOP Q BST GATE(H) COMP VFB Error Amp - + - + 0.8 V UVLO Comparator + SGND OC FF Reset Dominant R Q PGND ROSC VSTART VCC OC Comparator 60 mV IS- LGND + + IS+ 0.4 V Figure 2. NCP5211A Block Diagram - START OSC S START Q VC GATE(L) ROSC - - S + - Q COMP Comp http://onsemi.com 5 NCP5211A TYPICAL PERFORMANCE CHARACTERISTICS 31.5 31 30.5 CURRENT (mA) 30 29.5 29 28.5 28 27.5 27 26.5 -50 VREF, REFERENCE VOLTAGE (mV) 0 50 TEMPERATURE (C) 100 150 805 800 795 -50 0 50 TEMPERATURE (C) 100 150 Figure 3. COMP Source and Sink Current vs. Temperature CURRENT LIMIT THRESHOLD (mV) 62 1000 900 FREQUENCY (kHz) 61 800 700 600 500 400 300 200 58 -50 0 50 TEMPERATURE (C) 100 150 100 10 Figure 4. Reference Voltage vs. Temperature 60 59 20 30 40 50 60 70 80 90 100 110 120 ROSC (kW) Figure 5. Current Limit Threshold vs. Temperature 306 SWITCHING FREQUENCY (kHz) 304 302 300 298 296 294 292 290 288 286 284 -50 VCC SUPPLY CURRENT (mA) 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 -50 Figure 6. Switching Frequency vs. ROSC 0 50 TEMPERATURE (C) 100 150 0 50 TEMPERATURE (C) 100 150 Figure 7. Switching Frequency vs. Temperature ROSC = 51 kW Figure 8. VCC Supply Current vs. Temperature (Not Switching) http://onsemi.com 6 NCP5211A TYPICAL PERFORMANCE CHARACTERISTICS 4.2 4.18 4.16 THRESHOLD (V) 4.14 4.12 4.1 4.08 4.06 4.04 4.02 4 -50 STOP START MAX DUTY CYCLE (%) 100 150 71.5 71 70.5 70 69.5 69 68.5 -50 0 50 TEMPERATURE (C) 0 50 TEMPERATURE (C) 100 150 Figure 9. Start and Stop Threshold vs. Temperature Figure 10. Max Duty Cycle vs. Temperature http://onsemi.com 7 NCP5211A THEORY OF OPERATION V2t Control Method The V2 method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variations in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. PWM Comparator + GATE(H) GATE(L) associated with long feedback traces can be effectively filtered. Line and load regulations are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains a fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2 method of control maintains a fixed error signal for both line and load variations, since both line and load affect the ramp signal. Constant Frequency Operation Ramp Signal Error Amplifier Error Signal COMP - Figure 11. V2 Control Block Diagram The V2 control method is illustrated in Figure 11. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of the change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch from 0% to 70% duty cycle as required. A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2 control scheme to compensate the duty cycle. Since the change in the inductor current modifies the ramp signal, as in current mode control, the V2 control scheme has the same advantages in line transient response. A change in load current will have an effect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the fast feedback signal loop. The main purpose of this "slow" feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise + - Output Voltage Feedback Reference Voltage The NCP5211A uses a constant frequency, trailing edge modulation architecture for generating the PWM signal. During normal operation, the oscillator generates a narrow pulse at the beginning of each switching cycle to turn on the main switch. The main switch will be turned off when the ramp signal intersects with the output of the error amplifier (COMP pin voltage). Therefore, the switch duty cycle can be modified to regulate the output voltage to the desired value as line and load conditions change. The oscillator frequency of NCP5211A is programmable from 150 kHz to 750 kHz using an external resistor connected from the ROSC pin to SGND. Startup When VCC passes the UVLO voltage, the error amplifier starts charging the COMP pin capacitor. The output of the error amplifier (COMP voltage) will ramp up linearly. The COMP capacitance and the source current of the error amplifier determine the slew rate of the COMP voltage. The output of the error amplifier is connected internally to the inverting input of the PWM comparator and it is compared with the VFFB pin voltage plus a 0.5 V offset at the non-inverting input of the PWM comparator. Since VFFB voltage is zero before the startup, the PWM comparator output will stay high until the COMP pin voltage hits 0.5 V. There is no switching action while the PWM comparator output is high. After the COMP voltage exceeds the 0.5 V offset, the output of the PWM comparator toggles and releases the PWM latch. The narrow pulse generated by the oscillator at the beginning of the next oscillator cycle will set the latch so that the main switch is turned on and the regulator output voltage ramps up. When the output voltage reaches a level set by the COMP voltage, the main switch is turned off. The V2 control loop adjusts the main switch duty cycle as required to ensure the regulator output voltage tracks the COMP voltage. Gate Drive circuitry is enabled when VCOMP is greater than 0.4 V. This is to ensure switching http://onsemi.com 8 NCP5211A operation during ramp up. Since COMP voltage increases gradually, soft start can be achieved. The start-up period ends when the output voltage reaches the level set by the external resistor divider. Output Enable If the values of R and C are chosen such that: L + RC RL Then the voltage across the capacitor C will be: VC + RLIL Since there can be no switching until the COMP pin exceeds the 0.5 V offset built into the PWM comparator, the COMP pin can also be used for an enable function. Hold the COMP pin below 0.4 V with an open collector circuit to disable the output. When the COMP pin is released to enable startup, the user must ensure there is no leakage current from the enable circuit into COMP. During normal operation the COMP output is driven with only 5.0 A to 30 A internally. Cycle-by-Cycle Overcurrent Protection Under normal load conditions, the voltage across the IS+ and IS- pins is less than the 60 mV overcurrent threshold. If the threshold is exceeded, the present cycle is terminated by setting an overcurrent latch. While the latch is active, the comp voltage is prevented from rising. The latch is reset at the beginning of the next cycle and may be reset by the continuation of overcurrent. This set-reset cycle will continue until the overcurrent ceases. Inductor Current Sensing Besides using a current sense resistor to sense inductor current, NCP5211A provides the users with the possibility of using lossless inductor sensing as an alternative method in place of using a current sense resistor. This sensing technique utilizes the Equivalent Series Resistance (ESR) of the inductor to sense the current. The output current is sensed through an RC network in parallel with the inductor as shown in Figure 12. The voltage across the small capacitor is then fed to the OC comparator. IS+ VIN R C IS- Therefore, if the time constant of the RC network is equal to that of the inductor, the voltage across the capacitor is proportional to the inductor current by a factor of the inductor ESR. In practice, the user should ensure that under all component tolerances, the RC time constant is larger than the L/R time constant. This will keep the high frequency gain for VC(s)/IL(s) less than the low frequency gain, and avoid unnecessary OCP tripping during short duration overcurrent situations. Compared with conventional resistor sensing, the inductor ESR current sensing technique is lossless, but is not as accurate due to variation in the ESR from inductor to inductor and over temperature. For typical inductor ESR, the 0.39%/C positive temperature coefficient will reduce the current limit at high temperature, and will help prevent thermal runaway, but will force an increased design target at room temperature. This technique can be more accurate than using a PCB trace, since PCB copper thickness can vary 10-20%, compared to 1% variation in wire diameter thickness typical of inductors. Remote Voltage Sensing The NCP5211A has the capability to remotely sense the output voltage at the load when the load is located far away from the regulator. The SGND pin is dedicated to the differential remote sensing. The negative remote sense line is connected to the SGND pin directly, while the positive remote sense line is usually connected to the top of the feedback voltage divider. To prevent overvoltage conditions caused by open remote sense lines, the divider should also be locally connected to the output of the regulator through a low value resistor. That resistor is used to compensate for the voltage drop across the output power cables. Q1 L RL Q2 CO Figure 12. Inductor Current Sensing http://onsemi.com 9 NCP5211A APPLICATIONS INFORMATION APPLICATIONS AND COMPONENT SELECTION Inductor Component Selection Input Capacitor Selection and Considerations The output inductor may be the most critical component in the converter because it will directly effect the choice of other components and dictate both the steady-state and transient performance of the converter. When selecting an inductor, the designer must consider factors such as DC current, peak current, output voltage ripple, core material, magnetic saturation, temperature, physical size, and cost (usually the primary concern). In general, the output inductance value should be as low and physically small as possible to provide the best transient response and minimum cost. If a large inductance value is used, the converter will not respond quickly to rapid changes in the load current. On the other hand, too low an inductance value will result in very large ripple currents in the power components (MOSFETs, capacitors, etc.) resulting in increased dissipation and lower converter efficiency. Increased ripple currents will force the designer to use higher rated MOSFETs, oversize the thermal solution, and use more, higher rated input and output capacitors. The converter cost will be adversely affected. One method of calculating an output inductor value is to size the inductor to produce a specified maximum ripple current in the inductor. Lower ripple currents will result in less core and MOSFET losses and higher converter efficiency. The following equation may be used to calculate the minimum inductor value to produce a given maximum ripple current ( IO,MAX). The inductor value calculated by this equation is a minimum because values less than this will produce more ripple current than desired. Conversely, higher inductor values will result in less than the maximum ripple current. LoMIN + (Vin * Vout) @ Vout (a @ IO,MAX @ Vin @ fSW) The input capacitor is used to reduce voltage ripple caused by the current surges in the top pass transistor. The input current is pulsing at the switching frequency going from 0 to peak current in the inductor. The duty cycle will be a function of the ratio of the input to output voltage and of the efficiency. V D+ O VI 1 Eff The RMS value of the ripple into the input capacitors can now be calculated: IIN(RMS) + IOUT D * D2 The input RMS is maximum at 50% D, so selection of the possible duty cycle closest to 50% will give the worst case dissipation in the capacitors. The power dissipation of the input capacitors can be calculated by multiplying the square of the RMS current by the ESR of the capacitor. Output Capacitor is the ripple current as a percentage of the maximum output current ( = 0.15 for 15%, = 0.25 for 25%, etc) and fsw is the switching frequency. If the minimum inductor value is used, the inductor current will swing /2% about Iout. Therefore, the inductor must be designed or selected such that it will not saturate with a peak current of (1 + /2) IO,MAX. Power dissipation in the inductor can now be calculated from the RMS current level. The RMS of the ac component of the inductor is given by the following relationship: I IAC + PP 12 The output capacitor filters output inductor ripple current and provides low impedance for load current changes. The effect of the capacitance for handling the power supply induced ripple will be discussed here. Effects of load transient behavior can be considered separately. The principle consideration for the output capacitor is the ripple current induced by the switches through the inductor. This ripple current was calculated as IAC in the above discussion of the inductor. This ripple component will induce heating in the capacitor by a factor of the RMS current squared multiplied by the ESR of the output capacitor section. It will also create output ripple voltage. The ripple voltage will be a vector summation of the ripple current times the ESR of the capacitor, plus the ripple current integrating in the capacitor, and the rate of change in current times the total series inductance of the capacitor and connections. The inductor ripple current acting against the ESR of the output capacitor is the major contributor to the output ripple voltage. This fact can be used as a criterion to select the output capacitor. VPP + IPP CESR The power dissipation in the output capacitor can be calculated from: P + IAC2 CESR where IPP = IO,MAX. The total IRMS of the current will be calculated from: IRMS + IOUT2 ) IAC2 where: IAC = ac RMS current CESR = Effective series resistance of the output capacitor network. MOSFET & Heatsink Selection The power dissipation for the inductor can be determined from: P + IRMS2 ESR Power dissipation, package size, and thermal solution drive MOSFET selection. To adequately size the heat sink, the design must first predict the MOSFET power dissipation. http://onsemi.com 10 NCP5211A Once the dissipation is known, the heat sink thermal impedance can be calculated to prevent the specified maximum case or junction temperatures from being exceeded at the highest ambient temperature. Power dissipation has two primary contributors: conduction losses and switching losses. The control or upper MOSFET will display both switching and conduction losses. The synchronous or lower MOSFET will exhibit only conduction losses because it switches into nearly zero voltage. However, the body diode in the synchronous MOSFET will suffer diode losses during the non-overlap time of the gate drivers. For the upper or control MOSFET, the power dissipation can be approximated from: PD,CONTROL + (IRMS,CNTL2 @ RDS(on)) ) (ILo,MAX @ Qswitch Ig @ VIN @ fSW) ) (Qoss 2 @ VIN @ fSW) ) (VIN @ QRR @ fSW) ID VGATE VGS_TH QGS1 QGS2 QGD VDRAIN Figure 13. MOSFET Switching Characteristics The first term represents the conduction or IR losses when the MOSFET is ON while the second term represents the switching losses. The third term is the losses associated with the control and synchronous MOSFET output charge when the control MOSFET turns ON. The output losses are caused by both the control and synchronous MOSFET but are dissipated only in the control FET. The fourth term is the loss due to the reverse recovery time of the body diode in the synchronous MOSFET. The first two terms are usually adequate to predict the majority of the losses. Where IRMS,CNTL is the RMS value of the trapezoidal current in the control MOSFET: IRMS,CNTL + D @ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2 Ig is the output current from the gate driver IC. VIN is the input voltage to the converter. fsw is the switching frequency of the converter. QG is the MOSFET total gate charge to obtain RDS(on) (commonly specified in the data sheet). Vg is the gate drive voltage. QRR is the reverse recovery charge of the lower MOSFET. Qoss is the MOSFET output charge specified in the data sheet. For the lower or synchronous MOSFET, the power dissipation can be approximated from: PD,SYNCH + (IRMS,SYNCH2 @ RDS(on)) ) (Vfdiode @ IO,MAX 2 @ t_nonoverlap @ fSW) ILo,MAX is the maximum output inductor current: ILo,MAX + IO,MAX 2 ) DILo 2 The first term represents the conduction or IR losses when the MOSFET is ON and the second term represents the diode losses that occur during the gate non-overlap time. All terms were defined in the previous discussion for the control MOSFET with the exception of: IRMS,SYNCH + 1 * D @ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2 ILo,MIN is the minimum output inductor current: ILo,MIN + IO,MAX 2 * DILo 2 IO,MAX is the maximum converter output current. D is the duty cycle of the converter: D + VOUT VIN ILo is the peak-to-peak ripple current in the output inductor of value Lo: DILo + (VIN * VOUT) @ D (Lo @ fSW) RDS(on) is the ON resistance of the MOSFET at the applied gate drive voltage. Qswitch is the post gate threshold portion of the gate-to-source charge plus the gate-to-drain charge. This may be specified in the data sheet or approximated from the gate-charge curve as shown in the Figure 13. Qswitch + Qgs2 ) Qgd where: Vfdiode is the forward voltage of the MOSFET's intrinsic diode at the converter output current. t_nonoverlap is the non-overlap time between the upper and lower gate drivers to prevent cross conduction. This time is usually specified in the data sheet for the control IC. When the MOSFET power dissipations are known, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient operating temperature qT t (TJ * TA) PD where; T is the total thermal impedance (JC + SA). http://onsemi.com 11 NCP5211A JC is the junction-to-case thermal impedance of the MOSFET. SA is the sink-to-ambient thermal impedance of the heatsink assuming direct mounting of the MOSFET (no thermal "pad" is used). TJ is the specified maximum allowed junction temperature. TA is the worst case ambient operating temperature. For TO-220 and TO-263 packages, standard FR-4 copper clad circuit boards will have approximate thermal resistances (SA) as shown below: Pad Size (in2/mm2) 0.5/323 0.75/484 1.0/645 1.5/968 2.0/1290 2.5/1612 Single-Sided 1 oz. Copper 60-65C/W 55-60C/W 50-55C/W 45-50C/W 38-42C/W 33-37C/W response can be enhanced by the addition of a parallel combination of a resistor and capacitor between the COMP pin and the comp capacitor. ROSC Selection The switching frequency is programmed by selecting the resistor connected between the ROSC pin and SGND (pin 7). The grounded side of this resistor should be directly connected to the SGND pin, without any other currents flowing between the bottom of the resistor and the pin. Also, avoid running any noisy signals under the resistor, since injected noise could cause frequency jitter. The graph in Figure 6 shows the required resistance to program the frequency. Differential Remote Sense Operation As with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e. worst case MOSFET RDS(on)). Also, the inductors and capacitors share the MOSFET's heatsinks and will add heat and raise the temperature of the circuit board and MOSFET. For any new design, it is advisable to have as much heatsink area as possible. All too often, new designs are found to be too hot and require re-design to add heatsinking. Compensation Capacitor Selection The ability to implement fully differential remote sense is provided by the NCP5211A. The positive remote sense is implemented by bringing the output remote sense connection to the positive load connection. A low value resistor is connected from Vout to the feedback point at the regulator to provide feedback in the instance when the remote sense point is not connected. The negative remote sense connection is provided by connecting the SGND of the NCP5211A to the negative of the load return. Again, a low value resistor should be connected between SGND and LGND at the regulator to provide feedback in the instance when the remote sense point is not connected. The maximum voltage differential between the three grounds for this part is 200 mV. Feedback Divider Selection The feedback voltage measured at VFB during normal regulation will be 0.8 V. This voltage is compared to an internal 0.8 V reference and is used to regulate the output voltage. The bias current into the error amplifier is 1.0 A maximum, so select the resistor values so that this current does not add an excessive offset voltage. To take full advantage of the V2 control scheme, a small amount of output ripple is fed back to the VFFB pin. For most applications, the VFFB pin can be connected directly to the VFB pin. There are some applications that have to meet stringent load transient requirements. One of the key factors in achieving tight dynamic voltage regulation is low output capacitor ESR. Low ESR results in low output voltage ripple. This situation could result in increased noise sensitivity and a potential for loop instability. In applications where the output ripple is not sufficient, the performance of the NCP5211A can be improved by adding a fixed amount of external ramp compensation to the VFFB pin. Figure 14 shows how the amount of ramp at the VFFB pin depends on the switch node voltage, feedback voltage, R1 and C2. Vramp + (Vsw * VFB) ton (R1 C2) VFFB Feedback Selection The nominal output current capability of the error amp is 30 A. This current charging the capacitor on the COMP pin is used as soft start for the converter. The COMP pin will ramp up to a voltage level within 55 mV of what VFFB will be when in regulation. This is the voltage that will determine the soft start. Therefore, the COMP capacitor can be established by the following relationship: C + 30 mA soft start VFFB(REG) where: soft start = output ramp-up time VFFB(REG) = VFFB voltage when in regulation 30 A = COMP output current, typ. The COMP output current range is given in the data sheet and will affect the ramp-up time. The value of the capacitor on the COMP pin will have an effect on the loop response and the transient response of the converter. Transient http://onsemi.com 12 NCP5211A where: Vramp = amount of ramp needed; Vsw = switch note voltage; VFB = voltage feedback, 0.8 V; ton = switch on-time. To minimize the loss in efficiency, R1 resistance should be large, typically 100 kW or larger. With R1 chosen, C2 can be determined by the following; C2 + (Vsw * VFB) ton (R1 Vramp) should not be made too large, to reduce errors from bias current offsets. For typical L/R time constants, a 0.1 F capacitor for C1 will allow R2 to be between 1.0 k and 10 k. The current limit without R4 and R5, which are optional, is given by 60 mV/R1, where R1 is the internal resistance of the inductor, obtained from the manufacturer. The addition of R5 can be used to decrease the current limit to a value given by: ILIM + (60 mV * (VOUT R3 (R3 ) R5)) R1 C1 is used as a bypass capacitor and its value should be equal to or greater than C2. Vsw where VOUT is the output voltage. Similarly, omitting R5 and adding R4 will increase the current limit to a value given by: ILIM + 60 mV R1 (1 ) R2 R4) R1 C1 VFFB C2 R2 1.0 kW VFB Essentially, R4 or R5 are used to increase or decrease the inductor voltage drop which corresponds to 60 mV at the IS+ and IS- pins. IS- R3 R5 60 mV Trip Figure 14. Small RC Filter Providing the Proper Voltage Ramp at the Beginning of Each On-Time Cycle Maximum Frequency Operation IS+ R2 C1 R4 VOUT L1 L R1 Controller minimum pulse width limits the maximum operating frequency. The duty cycle, given by the output/input voltage ratio, multiplied by the period determines the pulse width during normal operation. This pulse width must be greater than 200 ns, or duty cycle jitter could occur. Current Sense Component Selection Switching Node Figure 15. Current Limit Boost Component Selection for Upper FET Gate Drive The current limit threshold is set by sensing a 60 mV voltage differential between the IS+ and IS- pins. Referring to Figure 15, the time constant of the R2,C1 filter should be set larger than the L/R1 time constant under worst case tolerances, to prevent overshoot in the sensed voltage and tripping the current limit too low. Resistor R3 of value equal to R2 is added for bias current cancellation. R2 and R3 The boost (BST) pin provides for application of a higher voltage to drive the upper FET. This voltage may be provided by a fixed higher voltage or it may be generated with a boost capacitor and charging diode, as shown in Figure 16. The voltage on the BST pin must be limited to 20 V. The 18 V zener in Figure 16 serves this purpose. http://onsemi.com 13 NCP5211A 12 V 12 V MMSZ4705ET1 0.1 F 18 V BAS21HT1 33 + 33 F/25 V x 3 NTMS7N03 2.9 H VC VCC COMP ROSC 0.1 F 51 k 0.1 F NCP5211A IS+ IS- SGND LGND VFFB VFB 1.0 k 1.0% 680 pF 5.23 k 1.0% SENSE+ BST GATE(H) GATE(L) PGND NTMS7N03 0.1 F 10 0.1 F 4.7 k + 5.0 V/8 A 100 F/10 V x 2 10 SENSE- NOTE: Resistance in Ohms Figure 16. Application Diagram, 12 V to 5.0 V/8 A Converter with Differential Remote Sense 12 V 5.0 V BAS21HT1 + 33 F/25 V x 3 NTMS7N03 0.22 F VC VCC COMP ROSC 0.1 F 51 k 0.1 F NCP5211A IS+ IS- SGND LGND VFFB VFB 1.0 k 1.0% 680 pF 3.16 k 1.0% SENSE+ BST GATE(H) GATE(L) PGND NTMS7N03 0.1 F 10 4.7 k + 2.9 H 3.3 V/8 A 100 F/10 V x 2 10 SENSE- NOTE: Resistance in Ohms Figure 17. Application Diagram, 12 V with 5.0 V Bias to 3.3 V/8 A Converter with Differential Remote Sense http://onsemi.com 14 NCP5211A BAS21HT1 MMSZ4705ET1 36 V - 72 V 2.2 F 18 V 100 W 51 kW BCP58-10T1 1 F 10 W 3.3 V/5 A 4.2 mH MMSZ4898T1 11 V U1 VC VCC ROSC COMP 1 F 0.1 F SGND LGND 51 kW GND BST GATE(H) GATE(L) PGND IS+ IS- VFFB VFB NCP5211A MTD8N20ET4 NTMS7N03 550 pF 3.16 kW NTMS7N03 100 pF 100 F/ 10 V x 2 0.1 W 10 W 1 kW GND Figure 18. Forward Converter Application, 3.3 V, 5 A Output Converter http://onsemi.com 15 NCP5211A PACKAGE DIMENSIONS SO-14 D SUFFIX CASE 751A-03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 8 -B- 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) K M M S J TB A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 V2 is a trademark of Switch Power, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 16 NCP5211A/D |
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